The IEC and other standards organizations have created standards for systems that communicate across or in potentially explosive environments. Such an atmosphere may exist in a high dust environment or an environment where flammable materials exist. Such standards specify the requirements for Intrinsic Safety (IS) circuits. Such IS circuits are prohibited from generating a spark or exceeding a certain temperature under shorted or other failure conditions. Techniques for designing an IS circuit include using components that limit currents and voltages (such as Zener diodes and series resistors), and using relatively small capacitors and inductors to reduce discharge voltages.
The combination of FIGS. 1A and 1B is an example of one type of prior art Power over Data Lines (PoDL) system (or single-pair Power over Ethernet (PoE) system) that uses IS techniques. FIG. 1A shows the power sourcing equipment (PSE) 10, and FIG. 1B shows the powered device (PD) 12. They are connected via a twisted wire pair or a coaxial cable connected to the media dependent interface (MDI) ports 14-17.
In the PSE 10, a voltage source 20 supplies the required power to the PD 12. A typical current is on the order of 400 mA, and a typical voltage is on the order of 14 volts DC. The currents and voltages are limited due to the IS criteria.
Inductors 22 and 24 pass the DC current but block AC signals, such as data and noise.
Diodes 26 and 28, when forward biased, limit the voltage drops across the inductors 22 and 24 to meet the IS criteria. Resistors 30 and 32 limit the current. Back-to-back Zener diodes 34 across the MDI ports 14 and 15 limit the voltage.
A PHY 36 outputs differential data and receives differential data. The PHY 36 represents the physical layer in the OSI model (Open Systems Interconnection model) and is a transceiver that typically includes signal conditioning and decoding circuitry for presenting bits to the next stage. The term PHY is a term of art and is defined by various IEEE standards (e.g., IEEE802.3cg), depending on the particular application. The PHY 36 is typically a commercially available integrated circuit. A digital processor (not shown) is coupled to the PHY 36, or is within the PHY 36, for processing the data.
AC-coupling capacitors 38 and 40 pass the AC data signals and block the DC voltage.
The resistors 42 and 44 are connected to the differential transmit terminals of the PHY 36 and have a relatively low value, such as 26.5 ohms. The resistors 46 and 48 are connected to the differential receive terminals of the PHY 36 and have a relatively high value, such as 2-10 kohms, to limit current.
A common mode choke (CMC) 49 is connected in series with the MDI ports 14 and 15.
The CMC 49 has magnetically coupled windings 50 and 51 having the same polarity. Any common mode noise on the wire pair is cancelled out (blocked) by the windings having the same polarity, while differential data and DC voltage are not substantially attenuated.
The PD 12 has DC and AC couplings generally similar to those of the PSE 10. A load (not shown) is connected across the ports 52 and 54 for receiving the voltage from the PSE 10 for powering the PD 12. The PHY 56 is also powered by the PSE 10. The resistors 58 and 60 in the differential transmit path are relatively low resistance, such as 50 ohms. The resistors 62 and 64 in the receive path have a relatively high resistance, such as 2-10 kohms.
Diodes 66 and 68, when forward biased, limit the voltage across the DC-coupling inductors 70 and 72. A full bridge rectifier 74 ensures the correct polarity of the DC voltage is applied to the load. Back-to-back Zener diodes 76 limit the voltage. A CMC 78 blocks common mode noise but passes the differential data and DC voltage. AC-blocking capacitors 80 and 82 pass the differential data but block the DC voltage.
Generally, the system of FIGS. 1A and 1B contain voltage and current limiters to prevent sparks and high temperatures occurring during fault conditions in accordance with the IS guidelines.
In some applications, it may be desirable to provide galvanic coupling (e.g., isolation transformer coupling) in the data path for improved DC blocking, improved common mode noise attenuation, improved safety, and improved reliability reasons. However, simply providing a separate transformer as an additional component in the data path may unduly inductively load the lines, add significant cost and size, and present additional possibilities for high discharge voltages that may create sparks.
Therefore, what is desirable is a configuration for a PoDL/PoE system that meets the IS guidelines yet uses galvanic coupling in the data path, where the configuration would not unduly inductively load the lines, not add significant cost and size, and not present additional possibilities for high discharge voltages that may create sparks. Ideally, the galvanic coupling feature would be integrated into the system so that existing components perform part of the function of the galvanic coupling and eliminate the various drawbacks of a separate transformer mentioned above.